An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration
| Autor: | Atieh Lotfi, Amir Yazdanbakhsh, Rajesh Gupta, Abbas Rahimi, Hadi Esmaeilzadeh |
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| Rok vydání: | 2017 |
| Předmět: |
Computer science
business.industry Data parallelism Approximation algorithm 02 engineering and technology Parallel computing computer.software_genre 020202 computer hardware & architecture Workflow Software 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Code generation Compiler Graphics Field-programmable gate array business computer |
| Zdroj: | From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators ISBN: 9783319537672 DATE |
| DOI: | 10.1007/978-3-319-53768-9_10 |
| Popis: | Modern applications including graphics, multimedia, web search, and data analytics not only can benefit from acceleration, but also exhibit significant degrees of tolerance to imprecise computation. This amenability to approximation provides an opportunity to trade quality of the results for higher performance and better resource utilization. Exploiting this opportunity is particularly important for FPGA accelerators that are inherently subject to many resource constraints. To better utilize the FPGA resources, we devise, Grater, an automated design workflow for FPGA accelerators that leverages imprecise computation to increase data-level parallelism and achieve higher computational throughput. The core of our workflow is a source-to-source compiler that takes in an input kernel and applies a novel optimization technique that selectively reduces the precision of kernel's data and operations. By selectively reducing the precision of the data and operation, the required area to synthesize the kernels on the FPGA decreases allowing to integrate a larger number of operations and parallel kernels in the fixed area of the FPGA. The larger number of integrated kernels provides more hardware context to better exploit data-level parallelism in the target applications. To effectively explore the possible design space of approximate kernels, we exploit a genetic algorithm to find a subset of safe-to-approximate operations and data elements and then tune their precision levels until the desired output quality is achieved. GRATER exploits a fully software technique and does not require any changes to the underlying FPGA hardware. We evaluate Grater on a diverse set of data-intensive OpenCL benchmarks from the AMD SDK. The synthesis result on a modern Altera FPGA shows that our approximation workflow yields 1.4×–3.0× higher throughput with less than 1% quality loss. |
| Databáze: | OpenAIRE |
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