Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
| Autor: | Hun-Hsien Chang, Tao Cheng, Chung-Yu Wu, Ming-Dou Ker |
|---|---|
| Rok vydání: | 1996 |
| Předmět: |
Capacitive coupling
Engineering Electrostatic discharge business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor Application-specific integrated circuit CMOS Hardware_GENERAL Hardware and Architecture Gate oxide law Low voltage cmos Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Software Hardware_LOGICDESIGN Voltage |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 4:307-321 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/92.532032 |
| Popis: | Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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