| Popis: |
With the ever decreasing transistor feature sizes, scaling of interconnect has caused many new challenges in fabrication technology. Three-dimensional (3D) geometrical effects due to mechanical stress and electrical charge on short-length or sharp-corner conductors and dielectrics has become more prominent in analyses of IC process variation, leakage current and reliability. In this paper modeling and characterization of 3D effects for etching and deposition, extended from physical models calibrated in 2D, will be discussed in view of boundary movement accuracy and robustness, and methodology for calibration with direct measurements. An L-shaped test structure will be used as a technology example. |
