| Autor: |
Chung-Nan Lee, Sheng-Yu Chiu, Tsung-Yu Ho, Ruei-Ting Gu, Ming-Chao Chiang, Chien-Chou Wang, Wen-Chi Shiue, Da-Jing Zhang-Jian, Tzu-Ching Tien, Jin-Hua Hong, Chung-Hua Tsai, Ing-Jer Huang, Shen-Fu Hsiao, Yun-Nan Chang, Wei-Sheng Huang |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT). |
| DOI: |
10.1109/vdat.2008.4542412 |
| Popis: |
A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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