A proposed FPGA-based parallel architecture for matrix multiplication

Autor:	B. Almashary, Shuja A. Abbasi, Syed Manzoor Qasim
Rok vydání:	2008
Předmět:	Logic synthesis Computer architecture Computer science Logic gate Multiplication Algorithm design Field-programmable gate array Reconfigurable computing Matrix multiplication FPGA prototype
Zdroj:	APCCAS
DOI:	10.1109/apccas.2008.4746382
Popis:	Matrix multiplication is a computation intensive operation and plays an important role in many scientific and engineering applications. For high performance applications, this operation must be realized in hardware. This paper presents a parallel architecture for the multiplication of two matrices using field programmable gate array (FPGA). The proposed architecture employs advanced design techniques and exploits architectural features of FPGA. Results show that it provides performance improvements over previously reported hardware implementation. FPGA implementation results are presented and discussed.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::54dfdb3f71606a048767c10ca2272d6f https://doi.org/10.1109/apccas.2008.4746382 Zobrazit plný text záznamu