A new route for cost-effective multi-process assembly of an optical silicon bench at the sub-micron accuracy

Autor: B. Paris, S. Rabaron, G. Lecarpentier
Rok vydání: 2004
Předmět:
Zdroj: IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).
DOI: 10.1109/iemt.2004.1321651
Popis: Assembly counts for a significant portion of the total cost of electronics devices. It is particularly true for optoelectronics devices as the majority of the assembly and packaging operations are still carried out manually. Cost reduction, linked to the integration of a larger number of elements into a single component is a preliminary condition to the deployment of optical networks in the telecommunications. Automation of the assembly improves processes reproducibility, increases yield and throughput and contributes to better control of the manufacturing cost. Planar technology is identified as a key enabling element of assembly automation. The integration of the optical components onto a silicon bench requires the use of a device bonder with flip chip capability and sub-micron placement accuracy. A particularity of the optoelectronics devices assembly is the need for using different processes for the various components being assembled with the same device. Bonding techniques such as thermo-compression, flux-less reflow and adhesive joining, together with very tight placement tolerance must be combined in a single assembly sequence. The paper describes the fully automatic assembly of an optical demonstrators consisting of a silicon bench on which are assembled various components: edge-emitting laser diode, photodiode, thermistance and cylindrical lens. A process mix is necessary: general reflow with self-alignment capability, in situ reflow and adhesive joining with 0.5/spl mu/m passive alignment accuracy. The assembly process is explained and the positive impact of high accuracy placement on the product performance is discussed. Furthermore, the use of the same platform and its high resolution stages (10nm) to perform active alignment by optimizing the signal output of a powered device is described.
Databáze: OpenAIRE