| Autor: |
D. K. Sohn, Y.K. Bae, Y.D. Lim, Yohan Kim, J.G. Hong, C. Ryou, Soon-yeon Park, C.G. Koh, Jae Gon Lee, Jung-Chak Ahn, S. Hyun, Byung-chan Lee, Sangjoo Lee, Yang-Soo Son, D.H. Cha, C.L. Cheng, Sung-dae Suk, S.W. Nam, H.-J. Cho, J.S. Yoon, Won-Jun Jang, M. Sadaaki, Ming Li, S.H. Hong, Wouns Yang, Sang-pil Sim, Dong-Won Kim, S. Choi, Jung-In Hong, Won-Cheol Jeong, B. U. Yoon, Hwa-Sung Rhee, Min-Sang Kim, Chilhee Chung, Daphnee Hui Lin Lee, Sang-Bom Kang, Kang-ill Seo, Hee-Soo Kang |
| Rok vydání: |
2011 |
| Předmět: |
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| Zdroj: |
2011 International Electron Devices Meeting. |
| DOI: |
10.1109/iedm.2011.6131556 |
| Popis: |
A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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