3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor
| Autor: | Tetsuo Nakano, Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, Hirozi Yamada, Y. Kobayashi, Tadaaki Bandoh, S. Tanaka |
|---|---|
| Rok vydání: | 1994 |
| Předmět: |
Adder
Floating point Reduced instruction set computing Comparator Computer science Circuit design Hardware_PERFORMANCEANDRELIABILITY Integrated circuit BiCMOS law.invention law Datapath Hardware_INTEGRATEDCIRCUITS Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Very-large-scale integration business.industry Sense amplifier Transistor FLOPS Microprocessor CMOS Embedded system business Computer hardware Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 29:298-302 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.278351 |
| Popis: | This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|