Modeling and Analysis of Parametric Yield under Power and Performance Constraints
| Autor: | Rajeev R. Rao, Dennis Sylvester, Anirudh Devgan, David Blaauw |
|---|---|
| Rok vydání: | 2005 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES Subthreshold conduction business.industry Fault tolerance Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design Application-specific integrated circuit Hardware and Architecture Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Software AND gate Hardware_LOGICDESIGN Leakage (electronics) Parametric statistics |
| Zdroj: | IEEE Design and Test of Computers. 22:376-385 |
| ISSN: | 0740-7475 |
| DOI: | 10.1109/mdt.2005.89 |
| Popis: | Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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