| Autor: |
Chi-Wu Huang, Zen-Yi Huang, Ying-Ping Lin, Teng-Kuei Hu, Chi-Jeng Chang |
| Rok vydání: |
2005 |
| Předmět: |
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| Zdroj: |
5th IEEE Conference on Nanotechnology, 2005.. |
| DOI: |
10.1109/nano.2005.1500725 |
| Popis: |
This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-seg and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device developed in another FPGA board was connected to the CPU as an image accelerator. By using the same way, other mechatronic or nano devices could also be connected to the CPU with proper designed controllers. The FPGA board could be used for teaching CPU design, controlling applications and also for system-on-chip (SoC) designing since all circuitries might be incorporated in a signal FPGA chip. A multifunctional platform is gradually evolving for teaching and applications. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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