Enhancing a hierarchical, parallel electron beam data conversion processor toward 1 Gbit memory lithography
| Autor: | K. Yano, S. Sakamoto, K. Koyama, S. Ohki, E. Murakami, S. Hara, S. Magoshi, T. Fujii, A. Kabeya, H. Suzuki, T. Saito, S. Watanabe |
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| Rok vydání: | 1995 |
| Předmět: |
Dynamic random-access memory
Data compaction business.industry Computer science General Engineering computer.file_format computer.software_genre law.invention Data conversion Optics Parallel processing (DSP implementation) Resist law Reticle Computer Aided Design business Lithography computer Computer hardware |
| Zdroj: | Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 13:2508 |
| ISSN: | 0734-211X |
| DOI: | 10.1116/1.588383 |
| Popis: | A new hierarchical, parallel electron beam (EB) data conversion system has been developed to be used in lithography for the fabrication of memories of 1 Gbit or more. The conversion system has been enhanced not only to meet EB writing requirements but also to cover new data processing capabilities required for critical dimension control and for optical resolution enhancement. The conversion system takes full advantage of the hierarchical, parallel technique and generates patterns for various EB lithography systems, including the EX‐8 mask writing system, EX‐8D wafer direct writing system, and MC‐100 defect inspection system. The interface with computer aided design (CAD) systems has been improved by realizing direct input from CADENCE Opus or Edge and from a design rule checker ENMA in addition to CALMA GDSII format. A design guide has been established to guarantee efficient, problem‐free hierarchical data conversion. Also, a new data compaction technique has been employed. The system is equipped with functions for increasing EB writing throughput. Moreover, functions for multipass writing and resize writing are available to improve pattern transfer fidelity in the resist development or chromium etching process. In the EB proximity effect correction, Ghost and dose modulation can be selectably used. For alternating phase shifting mask fabrication, a new CAD software to automatically assign shifter phase has been added. When a model 1 Gbit dynamic random access memory pattern with 0.15 μm minimum features designed following the design guide was scaled up for 4× reticle mask making and converted to the resize writing pattern on a workstation with four central processor units, the maximum conversion time per layer was 7 min 17 s, and an average conversion time was about 5 min. The data volume per mask amounted to 456 Mbytes. Using the compaction technique, the data volume was reduced to 1/7.7 at the maximum, and an average data compaction ratio of 4.5 was obtained. |
| Databáze: | OpenAIRE |
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