3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
| Autor: | D. McHerron, Katsuyuki Sakuma, Paul S. Andry, Cyril Cabral, Mukta G. Farooq, Rama Divakaruni, Thomas A. Wassick |
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| Rok vydání: | 2021 |
| Předmět: |
Materials science
Silicon Stacking chemistry.chemical_element Substrate (electronics) Chip Industrial and Manufacturing Engineering Line (electrical engineering) Die (integrated circuit) Electronic Optical and Magnetic Materials chemistry Soldering Electrical and Electronic Engineering Thin film Composite material |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:875-878 |
| ISSN: | 2156-3985 2156-3950 |
| Popis: | In this letter, we have demonstrated a packaging technique for 3-D IC with Cu back-end-of-the line (BEOL) on a mixed pitch (55 and $75~\mu \text{m}$ ) advanced ground-rule laminate by developing a 3-D die-stack on substrate (3D-DSS) technology. 3-D DSS is a new assembly technology to address issues caused by warpage and mechanical stress response of 3-D integration packaging when bonding a thin through-silicon via (TSV) die on an organic substrate. The $35\,\,\text {mm} \times 35$ mm test substrate has high density interconnects which include four wiring layers with thin film insulators on the chip mounting side of conventional buildup layers. A minimum 2 $\mu \text{m}$ /2 $\mu \text{m}$ line/space is constructed on this advanced ground-rule laminate. The experimental results showed that the 3-D DSS method can effectively prevent microbump opens or shorts, and can produce good solder joints between thin TSV die in a 3-D configuration on a fine, mixed pitch laminate. |
| Databáze: | OpenAIRE |
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