A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry
| Autor: | Sandeep Mishra, Md. Najrul Islam, Farhana Begum, Anup Dandapat |
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| Rok vydání: | 2019 |
| Předmět: |
Electronic speed control
Spurious-free dynamic range Comparator Computer science Capacitive sensing 020208 electrical & electronic engineering 020206 networking & telecommunications Successive approximation ADC 02 engineering and technology Dissipation Surfaces Coatings and Films Power (physics) CMOS Hardware and Architecture Signal Processing Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering |
| Zdroj: | Analog Integrated Circuits and Signal Processing. 100:311-325 |
| ISSN: | 1573-1979 0925-1030 |
| DOI: | 10.1007/s10470-019-01450-w |
| Popis: | Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work describes such a structure through the use of a novel low offset comparator thereby reducing the non-linearity performance along with significant improvement in energy-delay metric. A high speed control circuitry is introduced to improve the overall frequency of operation of SAR-ADC minimizing its speed limitation. Capacitive based digital-to-analog converter is used that switches in alternate cycles to reduce the static power dissipation. The ADC architecture is designed in 45-nm CMOS technology at layout of $$0.0139 \,{\hbox {mm}}^{2}$$ . The extracted results show that the proposed design is a reliable framework to ascertain the effectiveness of SAR-ADC with a faster performance. The results demonstrate an improvement of 47.75% in figure-of-merit. SNDR and SFDR are found to be 57.2 dB and 61.4 dB respectively at input frequency of 10 MHz. The sampling frequency is taken as 1 GHz with a power supply of 1 V. |
| Databáze: | OpenAIRE |
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