| Autor: |
A.C. Megdanis, K.R. Wrenner, H.J. Shin, Scott K. Reynolds, M. Immediato, Dale Jonathan Pearson, S. Gowda, R.L. Galbraith |
| Rok vydání: |
1995 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 30:1517-1523 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/4.482200 |
| Popis: |
This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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