A fast 7.5 ns access 1K-bit RAM for cache-memory systems
| Autor: | M. Suzuki, K. Kawarada, K. Toyoda, H. Mukai, Y. Kondo |
|---|---|
| Rok vydání: | 1978 |
| Předmět: |
Dynamic random-access memory
business.industry Computer science Sense amplifier CPU cache Reading (computer) Uniform memory access Registered memory Memory organisation Semiconductor memory law.invention Non-volatile memory law Computer data storage Hardware_INTEGRATEDCIRCUITS Interleaved memory Non-volatile random-access memory Electrical and Electronic Engineering Memory refresh business Computer memory Computer hardware |
| Zdroj: | IEEE Journal of Solid-State Circuits. 13:656-663 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A 1024-bit ECL RAM with greatly improved speed performances was developed. Typical access time and write cycle time are as short as 7.5 and 10 ns, respectively, under 784 mW of power dissipation, achieving a power and access-time product as small as 5.7 pJ/bit. Novel ECL circuit techniques, especially in address decoder circuits, as well as improved process technologies enabled realizing these high-speed characteristics. The device uses a V-groove isolation process and a shallow emitter diffusion technology with doped polysilicon. It has a memory organization of 256-words by 4-bits where its main use is as a cache memory. Besides this basic organization, it has flexibility to also operate as a 512-word by 2-bit and 1024-word by 1-bit memory. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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