A 109 GHz CMOS Power Amplifier With 15.2 dBm Psat and 20.3 dB Gain in 65-nm CMOS Technology
| Autor: | Dong Min Kang, Joo Young Jang, Hae Jin Lee, Chul Soon Park, Hyuk Su Son |
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| Rok vydání: | 2016 |
| Předmět: |
Power gain
Engineering business.industry Amplifier 020208 electrical & electronic engineering Transistor RF power amplifier Electrical engineering Power bandwidth 020206 networking & telecommunications 02 engineering and technology Condensed Matter Physics law.invention CMOS law Logic gate 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering business NMOS logic |
| Zdroj: | IEEE Microwave and Wireless Components Letters. 26:510-512 |
| ISSN: | 1558-1764 1531-1309 |
| Popis: | This letter presents a four-stage power amplifier (PA) with four-way transformer-based current combining using a standard 65 nm CMOS process. Each stage consists of common source (CS) topology with a capacitive cross-coupling neutralization to improve power gain, reverse isolation and AM-PM distortion. The power stage uses a diode connected NMOS transistor for linearity (AM-AM nonlinearity) enhancement. The proposed PA achieves a small-signal gain of 21 dB and 3-dB bandwidth of 17 GHz, output power of 12.5 dBm at a 1 dB compression point (OP1 dB) and a saturated output power of 15.2 dBm with a peak PAE of 10.3%. The total chip size including the pads and core chip size without the pads are 0.343 mm2 and 0.103 mm2, respectively. |
| Databáze: | OpenAIRE |
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