Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme
| Autor: | Inge Vaesen, Thomas Witters, Kristof Kellens, Anabela Veloso, Raja Athimulam, Aaron Thean, E. Vecchio, Farid Sebaai, Lars-Ake Ragnarsson, Hugo Bender, X. Shi, Katia Devriendt, A. Dangol, Vasile Paraschiv, Tom Schram, Thomas Chiarella, Stephan Brus, Harold Dekkers, Thierry Conard, Eddy Simoen, Moon Ju Cho, Annemie Van Ammel, Guillaume Boccardi, Soon Aik Chew, Olivier Richard, Nancy Heylen, Naoto Horiguchi, Jae Woo Lee, Higuchi Yuichi, Hiroaki Arimura, Philippe Roussel |
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| Rok vydání: | 2014 |
| Předmět: | |
| Zdroj: | Japanese Journal of Applied Physics. 53:04EA04 |
| ISSN: | 1347-4065 0021-4922 |
| DOI: | 10.7567/jjap.53.04ea04 |
| Popis: | We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (J G) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (N it) down to narrower fin devices [fin width (W Fin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |V T|, and substantially improved reliability behavior due to reduction of bulk defects. |
| Databáze: | OpenAIRE |
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