A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

Autor:	Hiroki Yamashita, Tatsuya Saito, Ryo Nemoto, Goichi Ono, Takashi Takemoto, Eiichi Suzuki, Noboru Masuda, Fumio Yuki, Koji Fukuda
Rok vydání:	2010
Předmět:	Engineering Demultiplexer Sense amplifier business.industry Electrical engineering Multiplexer Phase-locked loop CMOS Low-power electronics Electronic engineering Electrical and Electronic Engineering Transceiver business Clock recovery
Zdroj:	IEEE Journal of Solid-State Circuits. 45:2838-2849
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2010.2075410
Popis:	A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.
Databáze:	OpenAIRE
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