Implementation of a 3rd-generation SPARC V9 64 b microprocessor
| Autor: | R. Heald, K. Aingaran, C. Amir, M. Ang, M. Boland, A. Das, P. Dixit, G. Gouldsberry, J. Hart, T. Horel, null Wen-Jay Hsu, J. Kaku, null Chin Kim, null Song Kim, F. Klass, null Hang Kwan, null Roger Lo, H. McIntyre, A. Mehta, D. Murata, S. Nguyen, null Yet-Ping Pai, S. Patel, K. Shin, null Kenway Tam, S. Vishwanthaiah, J. Wu, null Gin Yee, null Hong You |
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| Rok vydání: | 2002 |
| Předmět: |
Instruction prefetch
Computer science Cache coloring Registered memory Cache pollution CAS latency law.invention Non-uniform memory access law Superscalar Hardware_INTEGRATEDCIRCUITS Interleaved memory Computing with Memory Static random-access memory Memory refresh Computer memory Dynamic random-access memory Hardware_MEMORYSTRUCTURES business.industry Uniform memory access Semiconductor memory Memory bandwidth Memory controller Tag RAM Shared memory Computer architecture Embedded system Cache business |
| Zdroj: | 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056). |
| DOI: | 10.1109/isscc.2000.839838 |
| Popis: | This 3rd-generation, superscalar processor, implementing the SPARC V9 64 b architecture, improves performance over previous processors by improvements in the on-chip memory system and circuit designs enhancing the speed of critical paths beyond the process entitlement. In the on-chip memory system, both bandwidth and latency are scaled. Keys to scaling memory latency are a sum-addressed memory data cache, which allows the average memory latency to scale by more than the clock ratio, and the use of a prefetch data cache. Memory bandwidth is improved by using wave-pipelined SRAM designs for on-chip caches and a write cache for store traffic. The chip operates at 800 MHz and dissipates |
| Databáze: | OpenAIRE |
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