Conception of a new LDPC decoder with hardware implementation on FPGA card
| Autor: | Hlou Laamari, Anas El Habti El Idrissi, Rachid El Gouri |
|---|---|
| Rok vydání: | 2014 |
| Předmět: |
Environmental Engineering
Computer science business.industry Berlekamp–Welch algorithm General Chemical Engineering Concatenated error correction code General Engineering Data_CODINGANDINFORMATIONTHEORY Serial concatenated convolutional codes Coding theory Computer Science::Hardware Architecture Hardware and Architecture Computer Science (miscellaneous) Turbo code Forward error correction Low-density parity-check code business Decoding methods Computer hardware Computer Science::Information Theory Biotechnology |
| Zdroj: | International Journal of Engineering & Technology. 3:451 |
| ISSN: | 2227-524X |
| DOI: | 10.14419/ijet.v3i4.3185 |
| Popis: | Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation. |
| Databáze: | OpenAIRE |
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