A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM
| Autor: | Chih-Wei Yao, Sang Won Son, Thomas Byunghak Cho, Ashutosh Verma, Yongrong Zuo, Kunal Godbole, Ivan Siu-Chuang Lu, Yongping Han, Pei-Yuan Chiang, Ronghua Ni, Wanghua Wu |
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| Rok vydání: | 2018 |
| Předmět: |
Physics
business.industry 020208 electrical & electronic engineering dBc 02 engineering and technology Phase-locked loop Sampling (signal processing) CMOS Duty cycle 0202 electrical engineering electronic engineering information engineering Calibration Figure of merit Optoelectronics business Jitter |
| Zdroj: | 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). |
| Popis: | We present a low jitter, DTC-based analog fractional-N PLL with novel, background DTC gain calibration and reference clock duty cycle correction for high performance applications. The PLL achieves a 75-fs rms jitter, integrated from 10 kHz to 10 MHz and a −249.7 dB figure of merit at fractional mode. The measured fractional-N spurs are less than −64 dBc across the 5.5-7.3 GHz output frequency. Implemented in 28-nm CMOS, this PLL consumes 18.9 mW and occupies 0.5 mm2. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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