Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture
| Autor: | Giovanni De Micheli, Shashikanth Bobba |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Materials science
business.industry Ambipolar diffusion Transistor Electrical engineering Nanowire 02 engineering and technology 021001 nanoscience & nanotechnology 020202 computer hardware & architecture law.invention CMOS Hardware and Architecture law Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Optoelectronics Electrical and Electronic Engineering Routing (electronic design automation) Physical design 0210 nano-technology business Software Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:2103-2115 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2014.2358884 |
| Popis: | As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits, thereby opening up venues for new transistor channel materials based on nanowires and nanotubes. Transistors based on nanowires and nanotubes inherently exhibit ambipolar behavior. While technologists aim to suppress ambipolar behavior of these transistors, new design methodologies are proposed by exploiting the phenomenon of controllable polarity. In this paper, we propose regular layout fabrics, with an emphasis on silicon nanowires (SiNWs) as the candidate technology. A double-gate ambipolar SiNW field-effect transistor operates as p-type or n-type by electrically controlling the polarity of the second gate. We propose layout techniques to address gate-level routing congestion, as every transistor has two gates to route. Novel symbolic layouts, which are technology independent, are proposed for ambipolar circuits. In the second part of this paper, we present an approach for designing an efficient regular layout called sea-of-tiles (SoTs). A logic tile is essentially an array of prefabricated transistor-pairs grouped together. We design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks onto the SoT fabric to find the optimum tile. This paper shows that SoT with $\mathrm{Tile}_{\mathit {G2}}$ and $\mathrm{Tile}_{\mathit {G1h2}}$ , on an average, outperforms the one with $\mathrm{Tile}_{\mathit {G1}}$ by 16% and 14% in area utilization, respectively. |
| Databáze: | OpenAIRE |
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