Circuit relevant HCS lifetime assessments at single transistors with emulated variable loads
| Autor: | Katja Puschkarsky, Christian Schlunder, Georg Georgakos, Fabian Proebster, Hans Reisinger, Jörg Berthold, Wolfgang Gustin |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Digital electronics Combinational logic Engineering Negative-bias temperature instability business.industry 020208 electrical & electronic engineering Transistor 02 engineering and technology Circuit reliability 01 natural sciences law.invention Reliability engineering Variable (computer science) law Logic gate 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Waveform business |
| Zdroj: | 2017 IEEE International Reliability Physics Symposium (IRPS). |
| Popis: | Hot carrier induced degradation of MOSFETs is still a concern for circuit reliability and not yet fully understood [1-4]. On the one hand stress measurements at single devices reveal critical parameter degradation for modern technologies especially at high VD=VG. On the other hand there are several publications stating that at least for combinational logic HCS plays only minor role for lifetime limits [e.g. 5]. In 2010 we have published experimental data of an integrated aging monitor demonstrating the small HCS impact on the lifetime of a critical logic path [6]. This discrepancy needs further investigation. An accurate circuit relevant assessment method is required to evaluate the correct HCS impact on lifetime. In this paper we introduce a new methodology to investigate and qualify product relevant HCS lifetime at single test devices with waveform AC-stress. We investigate the proportion of occurring device degradation mechanisms during digital circuit operations and clarify the different impact factors. Finally we compare the results of the new set-up in detail with the standard worst case approach based on experimental data in 130nm and 40nm technology nodes. |
| Databáze: | OpenAIRE |
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