16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
| Autor: | Alessandro Garghetti, Salvatore Levantino, Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Saleh Karman |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Phase-locked loop
CMOS Computer science 020208 electrical & electronic engineering 0202 electrical engineering electronic engineering information engineering Electronic engineering 020206 networking & telecommunications 02 engineering and technology Noise (electronics) Phase detector Sub-sampling Power (physics) Jitter |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2019.8662411 |
| Popis: | Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N frequency synthesizers in the sub-6GHz range, but, when used in the mm-wave range, at 30GHz and above, they typically feature poor jitter-power trade-off. This paper presents a 30GHz fractional-N DPLL in 65nm low-power (LP) CMOS achieving 198fs integrated jitter at 35mW power. The DPLL based on a digital-to-time converter (DTC) combines: (i) sub-sampling bang-bang phase detection to reduce power consumption, (ii) a digital error correction to reduce DTC noise contribution, and (iii) a low-power wide-lock-range divide-by-six circuit to allow operation up to 34GHz. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|