| Autor: |
Satish Parupalli, Deassy Novita, Gary Long, Todd Embree |
| Rok vydání: |
2012 |
| Předmět: |
|
| Zdroj: |
Volume 9: Micro- and Nano-Systems Engineering and Packaging, Parts A and B. |
| DOI: |
10.1115/imece2012-85562 |
| Popis: |
The continual drive toward smaller second level interconnect dimensions, along with the introduction of Halogen-Free circuit board materials and increased process temperatures of Lead-Free solders, have all contributed to a more frequent occurrence of Pad Crater damage in circuit board materials during manufacturing and test processes. This paper addresses the methodology and test data of some common industry methods used to evaluate Pad Crater strength in circuit board materials. Pad Crater test data is highly sensitive to sample design; as a result a discussion of sample design criteria is also included.Copyright © 2012 by ASME |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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