All-optical SR flip-flop based on SOA-MZI switches monolithically integrated on a generic InP platform
| Autor: | St. Pitris, Ch. Vagionas, R. Kisacik, George T. Kanellos, Tolga Tekin, R.G. Broeke, Nikos Pleros |
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| Rok vydání: | 2016 |
| Předmět: |
Optical amplifier
Computer science business.industry Electrical engineering 02 engineering and technology Die (integrated circuit) law.invention Footprint (electronics) 020210 optoelectronics & photonics Coupling (computer programming) law Embedded system Computer data storage Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Photonics business Waveguide Flip-flop |
| Zdroj: | SPIE Proceedings. |
| ISSN: | 0277-786X |
| DOI: | 10.1117/12.2211152 |
| Popis: | At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB. |
| Databáze: | OpenAIRE |
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