A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

Autor:	Yoshihiro Minami, Naoki Kusunoki, Akihiro Nitayama, Takeshi Hamamoto, Tomoaki Shino, Katsuyuki Fujita, A. Sakamoto, Hiroomi Nakajima, Takashi Ohsawa, T. Yamada, Mutsuo Morikado, K. Inoh, Tomoki Higashi, Kosuke Hatsuda
Rok vydání:	2007
Předmět:	Dynamic random-access memory Engineering business.industry Silicon on insulator Integrated circuit Electronic Optical and Magnetic Materials law.invention CMOS law Scalability Electronic engineering Electrical and Electronic Engineering business Dram Voltage Electronic circuit
Zdroj:	IEEE Transactions on Electron Devices. 54:563-571
ISSN:	0018-9383
Popis:	A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::4ec0ce53161450f59be76c3576054aef https://doi.org/10.1109/ted.2006.890597 Zobrazit plný text záznamu