Reduction of process temperature for Si surface flattening utilizing Ar/H2 ambient annealing and its application to SOI-MISFETs with bilayer HfN high-k gate insulator
| Autor: | Shin Ishimatsu, Yusuke Horiuchi, Shun-ichiro Ohmi, Sohya Kudoh |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Materials science Physics and Astronomy (miscellaneous) business.industry Annealing (metallurgy) Bilayer Transistor General Engineering General Physics and Astronomy Silicon on insulator Gate insulator Surface finish 01 natural sciences Flattening law.invention law 0103 physical sciences Optoelectronics business High-κ dielectric |
| Zdroj: | Japanese Journal of Applied Physics. 59:SCCB02 |
| ISSN: | 1347-4065 0021-4922 |
| DOI: | 10.7567/1347-4065/ab5173 |
| Popis: | We have investigated the reduction of process temperature for Si surface flattening process by the annealing in Ar/H2 ambient and its application to Si-on-insulator (SOI) metal-insulator-semiconductor field-effect transistors (MISFETs) with bilayer HfN high-k gate insulator. The surface root-mean-square (RMS) roughness of 0.057 nm was realized for the p-Si(100) substrates by the annealing at 925 oC/10 min in Ar/1.0%H2 ambient. Although the slip line defects were observed in the isolated SOI region after the optimized flattening process, the device characteristics of the fabricated SOI-MISFETs with HfN1.3/HfN1.1/Si(100) bilayer gate insulator was found to be improved by the surface flattening utilizing Ar/1.0%H2 annealing. |
| Databáze: | OpenAIRE |
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