| Autor: |
P. Gronowski, B. Cherkauer, Daniel W. Krueger, B. Stackhouse, C. Morganti, M.K. Gowan, Dave Bradley, E. Francom, S. Troyer, Christopher J. Bostak, Jayen J. Desai, Sal Bhimji |
| Rok vydání: |
2009 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 44:18-31 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/jssc.2008.2007150 |
| Popis: |
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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