A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications
| Autor: | Chris Vincent Densing, Arcel G. Leynes, Fredrick Angelo R. Galapon, Anastacia B. Alvarez, John Richard E. Hizon, Maria Theresa de Leon, Mark Allen D. C. Agaton, Lemuel Neil M. Noveno, Marc Rosales, Rico Jossel M. Maestro |
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| Rok vydání: | 2018 |
| Předmět: |
Battery (electricity)
business.industry Computer science 020208 electrical & electronic engineering Electrical engineering Process (computing) 02 engineering and technology Synchronization 020202 computer hardware & architecture Power (physics) Phase-locked loop 0202 electrical engineering electronic engineering information engineering Wireless Clock generator business Phase frequency detector Wireless sensor network Electronic circuit |
| Zdroj: | TENCON |
| DOI: | 10.1109/tencon.2018.8650488 |
| Popis: | Due to the limited energy supply of wireless sensor nodes, minimizing their power consumption has become a primary concern to increase their battery lives. These sensor nodes require clock signals to process data and to synchronize with other sensor nodes in the network. However, clock generator circuits usually consume a lot of power. This work addresses this problem by implementing a low-power all-digital phase-locked loop (ADPLL) in a 65nm CMOS process with a low operating voltage of 0.5V. Its output frequency range is 0.285 – 48MHz with a power consumption of 8.25µW at 23MHz. With the use of the frequency estimation algorithm, the ADPLL is able to achieve fast lock-in time within 5 reference clock cycles with frequency errors of less than 1.5%. |
| Databáze: | OpenAIRE |
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