| Autor: |
Ralph Bellofatto, S. M. Douskey, Martin Ohmacht, T. A. Liebsch, Dirk Hoenicke, Paul G. Crumley, M. R. Ellavsky, R. A. Haring, B. Gopalsamy, M. B. Dombrowa, J. A. Marcella, A. A. Bright |
| Rok vydání: |
2005 |
| Předmět: |
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| Zdroj: |
IBM Journal of Research and Development. 49:289-301 |
| ISSN: |
0018-8646 |
| DOI: |
10.1147/rd.492.0289 |
| Popis: |
The Blue Gene®/L compute (BLC) and Blue Gene/L link (BLL) chips have extensive facilities for control, bring-up, self-test, debug, and nonintrusive performance monitoring built on a serial interface compliant with IEEE Standard 1149.1. Both the BLL and the BLC chips contain a standard eServer™ chip JTAG controller called the access macro. For BLC, the capabilities of the access macro were extended 1) to accommodate the secondary JTAG controllers built into embedded PowerPC® cores; 2) to provide direct access to memory for initial boot code load and for messaging between the service node and the BLC chip; 3) to provide nonintrusive access to device control registers; and 4) to provide a suite of chip configuration and control registers. The BLC clock tree structure is described. It accommodates both functional requirements and requirements for enabling multiple built-in self-test domains, differentiated both by frequency and functionality. The chip features a debug port that allows observation of critical chip signals at full speed. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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