| Popis: |
Evolution of semiconductor packaging has taken impressive acceleration, under the pressure of new applications, combining very high volumes, innovation and cost effectiveness. Conventional single chip package completed its cycle, by reaching a die-to-package ratio close to one. And also wire bonding technology is getting close to its physical limits, at about 25-30 micron bonding pad pitch. New 3D interconnection technologies, like System in Package (SiP), Package on Package (PoP) and, Package in Package (PiP), offer the unique advantage of integrating heterogeneous functions in the three dimensions of the package, which can be in some extent competitive with chip-level integration (System on Chip — SoC). But this is not enough: the need of further miniaturization promotes the industrialization of new platforms, like the "chip in laminate", where the active chips are embedded in the organic substrate of the 3D system, and the "system on silicon" where the 3D structure is obtained on silicon wafers as first level carrier. All new 3D techniques have tremendous impact on manufacturing; will require the development of new machines and materials; will cause major changes in the organization of design and production, with unprecedented integration among wafer fab, assembly, testing. |
