| Autor: |
Wennan Feng, Lijiu Ji, Zhongjian Chen, Song Jia, Yan Ge |
| Rok vydání: |
2006 |
| Předmět: |
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| Zdroj: |
2005 6th International Conference on ASIC. |
| DOI: |
10.1109/icasic.2005.1611343 |
| Popis: |
Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented in this paper. The proposed topology uses only one adaptive phase frequency detector (PFD) and controllable charge pumps to realize adaptive bandwidth scheme. With a SMIC standard 0.25mum 1P5M 2.5V CMOS logic process, the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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