| Autor: |
C. Amir, D. Vo, D. Pini, A. Kowalczyk, Xin Liu, Sung-Hun Oh, Baoqing Huang, V. Adler, S. Kumar, Sourav Ghosh, Lan Lee, B. Sur, Allan Tzeng, N.G. Malur, Yuefei Ge, Chung Lau, W.J. de Lange, S. Zambare, Y.S. Kao, Cong Khieu, Jin Zong, F. Chiu, A. Liebermensch, Tan Hoang, S. Dubler, I. Orginos, Choon Chug, L. Shih, R. Hu, Suman Kant, Hiep Ngo |
| Rok vydání: |
2002 |
| Předmět: |
|
| Zdroj: |
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177). |
| DOI: |
10.1109/isscc.2001.912619 |
| Popis: |
The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing 0.22 /spl mu/m CMOS with all-Cu interconnect. Two CPUs, delivering GGFLOPS and 13GOPS at 500 MHz, are tightly coupled through a shared, coherent, 4-way set associative 16 KB data cache, and an on-chip 4 GB/s switch. Each CPU is a 4-issue VLIW engine. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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