A Configurable FPGA Implementation of PEG-based PS-LDPC Decoder
| Autor: | Ningqing Liu, Bin Sun, Hao-wei Sun, Kun Wang |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Signal processing
Computer science business.industry Data_CODINGANDINFORMATIONTHEORY Parallel computing Computer Science::Hardware Architecture Error correcting Algorithm design Shift matrix Low-density parity-check code business Field-programmable gate array Computer hardware Decoding methods Computer Science::Information Theory Coding (social sciences) |
| Zdroj: | 2010 First International Conference on Pervasive Computing, Signal Processing and Applications. |
| Popis: | Low-density parity-check (LDPC) codes form an important subclass of error correcting coding techniques, and its implementation has been hot spot of domains such as signal process, magnetic recording or next generation communication for years. This paper proposes a configurable FPGA implementation of Partition-and-Shift LDPC decoder based on Min-Sum algorithm. An MPEG algorithm is introduced to reduce the complexity of searching for closed paths in shift matrix. And a routing paths switch concept is proposed to realize the expected configurability. Benefits of the proposed technique are demonstrated with FPGA design for differently configured PS-LDPC decoders which all achieve a Gbps throughput, low hardware cost and excellent BER performance at 16 iterations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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