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The integration scale in one chip in the last decades has improved dramatically, highlighting in the same time critical reliability issues. Run-time mechanisms that correct errors in real-time deal ensure the operation reliability, availability, and serviceability (RAS), paying a price in performance as expressed in extra clock cycles. The system scenario concept can contribute to improve these mechanisms exploiting a flexibility decision-making scheme. The current section deploys such a run-time mechanism that mitigates the correction overhead, guaranteeing the performance dependability. As discussed in ch_DVFS we have developed a quite broad range of DVFS configuration knob oriented scenario approaches. These will be partly exploited also here. In this direction, a closed-loop controller absorbs the RAS-induced delay by triggering dynamic voltage and frequency scaling (DVFS) schemes. We go a step-forward of the generic scenario methodology importing the meaning of the scenarios adaptation in operation norms after the definition of an initial scenario set. More precisely, in the current chapter we focus on the run-time adjustment of the DVFS responses to the identified performance variability norms. To achieve this, we exploit an adaptive scenario scheduler that reorganizes the scenario hierarchy at run-time. Compared against an approach utilizing a 30% operation frequency guardband, the proposed configuration achieves an 83.9% exploitation of the nominal improvement margins that corresponds to an energy gain up to 15%, ensuring to a large extent the performance dependability. |
