A partitioning-free methodology for optimized gate-level monolithic 3D designs

Autor:	O. Billoint, Hossam Sarhan, Sebastien Thuries, G. Berhault, M. Brocard
Rok vydání:	2017
Předmět:	Footprint (electronics) Computer science Margin (machine learning) Switching power Fast Fourier transform Benchmark (computing) Low-density parity-check code Computational science
Zdroj:	2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
DOI:	10.1109/s3s.2017.8309221
Popis:	This paper presents a partitioning-free algorithm that transforms a 2D design into a gate-level Monolithic 3D one, reducing design footprint by 50%, total wire length by 15% and net switching power by at least 30% around iso-performance (considered with a 5% margin) for all the benchmark blocks (openMSP, FFT, LDPC and 128-bits AES) in 28nm technology.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::4ca1bce028aaea07b5bdb0a30bad9916 https://doi.org/10.1109/s3s.2017.8309221 Zobrazit plný text záznamu