SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
| Autor: | Moinuddin K. Qureshi, Gururaj Saileshwar, Wendy Arnott Elsasser, Ramrakhyani Prakash S, Prashant J. Nair |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Speedup Memory errors Computer science business.industry 02 engineering and technology Encryption 01 natural sciences 020202 computer hardware & architecture Memory management Data access Embedded system 0103 physical sciences Memory architecture 0202 electrical engineering electronic engineering information engineering Message authentication code business Error detection and correction |
| Zdroj: | HPCA |
| Popis: | Building trusted data-centers requires resilient memories which are protected from both adversarial attacks and errors. Unfortunately, the state-of-the-art memory security solutions incur considerable performance overheads due to accesses for security metadata like Message Authentication Codes (MACs). At the same time, commercial secure memory solutions tend to be designed oblivious to the presence of memory reliability mechanisms (such as ECC-DIMMs), that provide tolerance to memory errors. Fortunately, ECC-DIMMs possess an additional chip for providing error correction codes (ECC), that is accessed in parallel with data, which can be harnessed for security optimizations. If we can re-purpose the ECC-chip to store some metadata useful for security and reliability, it can prove beneficial to both. To this end, this paper proposes Synergy, a reliability-security co-design that improves performance of secure execution while providing strong reliability for systems with 9-chip ECC-DIMMs. Synergy uses the insight that MACs being capable of detecting data tampering are also useful for detecting memory errors. Therefore, MACs are best suited for being placed inside the ECC chip, to be accessed in parallel with each data access. By co-locating MAC and Data, Synergy is able to avoid a separate memory access for MAC and thereby reduce the overall memory traffic for secure memory systems. Furthermore, Synergy is able to tolerate 1 chip failure out of 9 chips by using a parity that is constructed over 9 chips (8 Data and 1 MAC), which is used for reconstructing the data of the failed chip. For memory intensive workloads, Synergy provides a speedup of 20% and reduces system Energy Delay Product by 31% compared to a secure memory baseline with ECC-DIMMs. At the same time, Synergy increases reliability by 185x compared to ECC-DIMMs that provide Single-Error Correction, Double-Error Detection (SECDED) capability. Synergy uses commercial ECC-DIMMs and does not incur any additional hardware overheads or reduction of security. |
| Databáze: | OpenAIRE |
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