| Autor: |
Yang Wang, Lin-lin Xie, Shu-shan Qiao |
| Rok vydání: |
2016 |
| Předmět: |
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| Zdroj: |
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). |
| Popis: |
A portable counter-assisted all-digital phase-locked loop (ADPLL) with fast settling time is presented in this paper. A wide-frequency-range and high-resolution interpolating digitally controlled oscillator (IDCO) is proposed to satisfy target frequency requirements. Three settling processes with different kinds of loop filters enable both fast settling time and low jitter. The proposed ADPLL has been fabricated in 180 nm CMOS technology with active area of 0.9um2. The measured output frequency of the ADPLL ranges from 294MHz to 730MHz. The settling time is only 15us at reference frequency of 10MHz. The integrated phase noise (rms jitter) from 100kHz to 10MHz is 22.14ps. The power consumption is 8mW at 294MHz and 15mW at 730MHz. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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