Influence of Post-Annealing on Electrical Characteristics of Thin-Film Transistors with Atomic-Layer-Deposited ZnO-Channel/Al 2 O 3 -Dielectric
Autor: | Shi-Jin Ding, Li-Li Zheng, You-Hang Wang, Wei Zhang, Qian Ma, Wen-Jun Liu, Hong-Liang Lu |
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Rok vydání: | 2016 |
Předmět: |
010302 applied physics
Materials science Annealing (metallurgy) business.industry Transistor General Physics and Astronomy 02 engineering and technology Dielectric Electron 021001 nanoscience & nanotechnology 01 natural sciences Bias stress law.invention Post annealing law Thin-film transistor 0103 physical sciences Thermal Optoelectronics 0210 nano-technology business |
Zdroj: | Chinese Physics Letters. 33:058501 |
ISSN: | 1741-3540 0256-307X |
DOI: | 10.1088/0256-307x/33/5/058501 |
Popis: | High-performance thin-film transistors (TFTs) with a low thermal budget are highly desired for flexible electronic applications. In this work, the TFTs with atomic layer deposited ZnO-channel/Al2O3-dielectric are fabricated under the maximum process temperature of 200°C. First, we investigate the effect of post-annealing environment such as N2, H2-N2 (4%) and O2 on the device performance, revealing that O2 annealing can greatly enhance the device performance. Further, we compare the influences of annealing temperature and time on the device performance. It is found that long annealing at 200°C is equivalent to and even outperforms short annealing at 300°C. Excellent electrical characteristics of the TFTs are demonstrated after O2 annealing at 200°C for 35 min, including a low off-current of 2.3 × 10−13 A, a small sub-threshold swing of 245 mV/dec, a large on/off current ratio of 7.6×108, and a high electron effective mobility of 22.1 cm2/Vs. Under negative gate bias stress at − 10 V, the above devices show better electrical stabilities than those post-annealed at 300°C. Thus the fabricated high-performance ZnO TFT with a low thermal budget is very promising for flexible electronic applications. |
Databáze: | OpenAIRE |
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