A Framework for the Automatic Vectorization of Parallel Sort on x86-Based Processors
| Autor: | Hao Wang, Kaixi Hou, Wu-chun Feng |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
020203 distributed computing
Speedup Computer science Sorting 020207 software engineering 02 engineering and technology Parallel computing Ivy Bridge Instruction set Computational Theory and Mathematics Hardware and Architecture Transpose Signal Processing 0202 electrical engineering electronic engineering information engineering Sorting network sort x86 |
| Zdroj: | IEEE Transactions on Parallel and Distributed Systems. 29:958-972 |
| ISSN: | 1045-9219 |
| DOI: | 10.1109/tpds.2018.2789903 |
| Popis: | The continued growth in the width of vector registers and the evolving library of intrinsics on the modern x86 processors make manual optimizations for data-level parallelism tedious and error-prone. In this paper, we focus on parallel sorting, a building block for many higher-level applications, and propose a framework for the Automatic SIMDization of Parallel Sorting (ASPaS) on x86-based multi- and many-core processors. That is, ASPaS takes any sorting network and a given instruction set architecture (ISA) as inputs and automatically generates vector code for that sorting network. After formalizing the sort function as a sequence of comparators and the transpose and merge functions as sequences of vector-matrix multiplications, ASPaS can map these functions to operations from a selected “pattern pool” that is based on the characteristics of parallel sorting, and then generate the vector code with the real ISA intrinsics. The performance evaluation on the Intel Ivy Bridge and Haswell CPUs, and Knights Corner MIC illustrates that automatically generated sorting codes from ASPaS can outperform the widely used sorting tools, achieving up to 5.2x speedup over the single-threaded implementations from STL and Boost and up to 6.7x speedup over the multi-threaded parallel sort from Intel TBB. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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