The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process
| Autor: | Po-Ying Chen, T.-C. Lin, Ming-Hsiung Tsai, Shen-Li Chen, M.H. Jing |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Materials science
Yield (engineering) business.industry Hardware_PERFORMANCEANDRELIABILITY Chip Barrier layer CMOS Nanoelectronics Hardware_GENERAL Hardware_INTEGRATEDCIRCUITS Electronic engineering Optoelectronics Node (circuits) Dry etching business Failure mode and effects analysis Hardware_LOGICDESIGN |
| Zdroj: | 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits. |
| DOI: | 10.1109/ipfa.2007.4378097 |
| Popis: | CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called "cosmetic defects" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|