Design of High-Performance CMOS Level Converters Considering PVT Variations
| Autor: | Yu-Juey Chang, Jinn-Shyan Wang, Chingwei Yeh |
|---|---|
| Rok vydání: | 2011 |
| Předmět: |
Engineering
Input offset voltage business.industry Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Converters Electronic Optical and Magnetic Materials law.invention CMOS law Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering System on a chip Electrical and Electronic Engineering business Low voltage Voltage |
| Zdroj: | IEICE Transactions on Electronics. :913-916 |
| ISSN: | 1745-1353 0916-8524 |
| Popis: | CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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