| Autor: |
Hiroshi Mawatari, Hiroyuki Nagano, Satoru Kuramochi, Yoshitaka Fukuoka, Sumio Koiwa, Kousuke Suzuki, Jiro Iida, Miyuki Akazawa |
| Rok vydání: |
2016 |
| Předmět: |
|
| Zdroj: |
2016 Pan Pacific Microelectronics Symposium (Pan Pacific). |
| DOI: |
10.1109/panpacific.2016.7428426 |
| Popis: |
As electronic products becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of silicon and glass interposers with fine pitch metalized through via. High frequency transmission characteristics were measured with TSV and TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000 cycle from −40 Celsius deg to 80 Celsius deg. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
