Novel parasitic-SCR impacts on ESD robustness in the 60 V power pLDMOS devices
| Autor: | Yi-Cih Wu, Yi-Hao Chiu, Jia-Ming Lin, Chih-Ying Yen, Yi-Hao Chao, Chih-Hung Yang, Kuei-Jyun Chen, Chun-Ting Kuo, Yu-Lin Lin, Hung-Wei Chen, Jen-Hao Lo, Shen-Li Chen |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science business.industry Robustness (computer science) 020208 electrical & electronic engineering 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electrical engineering 02 engineering and technology business 01 natural sciences |
| Zdroj: | 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW). |
| DOI: | 10.1109/icce-china.2017.7991155 |
| Popis: | The pLDMOS related devices fabricated by a TSMC 0.25 µm 60 V process was investigated in this paper. For the ESD improvement, some DUTs inserting the N+ zone to form an embedded SCR in the drain end or guard-ring area, respectively. From the TLP testing results, the I t2 values of the drain parasitic SCR npn-type and pnp-type could reach > 7 A, higher than that of the traditional pLDMOS device. However, the V t1 and V h values of the pLDMOS-SCR npn-type were less than that of the pnp-type. Furthermore, the V h value of the pLDMOS-SCR (ring pn-type) was higher than that of the pLDMOS-SCR (ring pn-type_Del co) for the high immunity of latch-up effect. The I t2 capability of pLDMOS-SCR (ring pn-type) can reach 3.223 A, then as compared with the traditional pLDMOS increased about 251.8%. Therefore, the pLDMOS-SCR (ring pn-type) is a nice layout manner for the ESD robustness and anti-latch-up immunity. |
| Databáze: | OpenAIRE |
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