| Autor: |
Seung-Jun Bae, Jongwook Park, Young-Soo Sohn, Taesung Kim, Sewon Eom, Young-Seok Kim, Hyuck-Joon Kwon, Daesik Moon, Seong-Hwan Kim, Ki-Ho Kim, Seungseob Lee, Eungsung Seo, Jin-Hyeok Baek, Yoon-Joo Eom, Kyoung-Ho Kim, Jung-Hwan Choi, Tae-Young Oh, Gil-Hoon Cha, Seok-Hun Hyun, Yoon-Gyu Song, Youn-sik Park, Kyung-Soo Ha, Young Hoon Son, Dae-Hee Jung, In-Dal Song, Kwang-Il Park, Hyunyoon Cho, Bo-Tak Lim, Chang-Kyo Lee, Si-Hyeong Cho, Joon-Young Park, Junha Lee, Jin-Seok Heo, Young-Ryeol Choi, Seong-Jin Jang |
| Rok vydání: |
2017 |
| Předmět: |
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| Zdroj: |
A-SSCC |
| DOI: |
10.1109/asscc.2017.8240239 |
| Popis: |
This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the supply-voltage variations which are caused by dynamic voltage frequency switching (DVFS) and alleviates the calibration time which is increased by insertion of additional CA calibration. The offset of a comparator is averaged out by fraction-referred input switching-then-averaging scheme (FISA). And code-referred periodic ZQ update (CPZU) scheme can track the VT variation while minimizing the interference. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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