Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test
| Autor: | Yuta Yamato, Seiji Kajihara, Hans-Joachim Wunderlich, Stefan Holst, Xiaoqing Wen, Eric Schneider, Michael A. Kochte |
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| Rok vydání: | 2016 |
| Předmět: |
Pass transistor logic
Computer science Accurate estimation Real-time computing 0211 other engineering and technologies Clock tree 02 engineering and technology 020202 computer hardware & architecture Logic gate Dynamic demand 0202 electrical engineering electronic engineering information engineering Power network design Algorithm 021106 design practice & management |
| Zdroj: | ATS |
| DOI: | 10.1109/ats.2016.49 |
| Popis: | IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming electrical simulations. |
| Databáze: | OpenAIRE |
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