Bitwidth customization in image processing pipelines using interval analysis and SMT solvers
| Autor: | Uday Bondhugula, Vinamra Benara, Suresh Purini, Ziaul Choudhury |
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| Rok vydání: | 2020 |
| Předmět: |
050101 languages & linguistics
Computer science Pipeline (computing) 05 social sciences Image processing 02 engineering and technology Parallel computing computer.software_genre Data type Interval arithmetic 0202 electrical engineering electronic engineering information engineering Benchmark (computing) 020201 artificial intelligence & image processing 0501 psychology and cognitive sciences Compiler Tuple Greedy algorithm computer |
| Zdroj: | CC |
| DOI: | 10.1145/3377555.3377899 |
| Popis: | Unlike CPUs and GPUs, it is possible to use custom fixed-point data types, specified as a tuple (α, β), on FPGAs. The parameters α and β denote the number of integral and fractional bitwidths respectively. The power and area savings while performing arithmetic operations on fixed-point data types are well known to be significant over using floating-point data types. In this paper, we propose a hybrid approach involving interval analysis and SMT solvers, for estimating integral bitwidths at different compute stages, in an image processing pipeline, specified using a domain-specific language (DSL) such as PolyMage. The DSL specification facilitates the compiler analysis to infer the underlying computational structure with ease. We also propose a simple and practical profile-driven greedy heuristic search technique for fractional bitwidth analysis. Using the Horn-Schunck Optical Flow benchmark program, we demonstrate where the conventional range analysis approaches fail, and how we overcome them using the hybrid technique proposed in this paper. The integral bitwidth estimates provided by the hybrid technique on the optical flow benchmark are up to 3x times better when compared with interval analysis. |
| Databáze: | OpenAIRE |
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