Optimization of logarithmic converter for LNS based SOC
| Autor: | A. T. A. Kishore Kumar, R. Seshasayanan |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Digital electronics
Signal processing Floating point Computer Networks and Communications business.industry Computer science 020206 networking & telecommunications 02 engineering and technology Reduction (complexity) 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Multiplication Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Software Computer hardware Electronic circuit |
| Zdroj: | Cluster Computing. 22:12759-12766 |
| ISSN: | 1573-7543 1386-7857 |
| Popis: | As FPGAs and ASICs are widely used for floating point computationally intensive operations, a logarithmic converter focusing on reducing the computational complexity and easy to implement is presented in this paper. The logarithmic converter is a part of LNS based SoC which is used for image processing and signal processing applications. The LNS based reconfigurable processor basically converts intensive computations like multiplication, division etc., into a series of addition and subtraction, hence making into simple operation realizable using digital circuits. FPGAs are inherently parallel and reducing the computational complexity will further improve the speed of execution of the algorithm intended. To start with, we have optimized the initial level circuits like LOD and LOPD which is a major part of the logarithmic converter. Optimizing these circuits yield a significant reduction in the conversion time. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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