Balanced application-specific processor system for efficient SIFT-feature detection
| Autor: | Nico Mentzer, Julian Hartig, Holger Blume, Guillermo Paya-Vaya |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
0209 industrial biotechnology
Coprocessor Computer science Design space exploration business.industry Feature extraction 02 engineering and technology 020901 industrial engineering & automation Very long instruction word Feature (computer vision) 0202 electrical engineering electronic engineering information engineering Hardware acceleration 020201 artificial intelligence & image processing business Field-programmable gate array Computer hardware Feature detection (computer vision) |
| Zdroj: | SAMOS |
| DOI: | 10.1109/samos.2017.8344614 |
| Popis: | Due to its computational complexity, the Scale-Invariant Feature Transform (SIFT) algorithm poses a challenge for use in embedded applications. To meet real-time at low power, hardware acceleration is necessary. This paper presents an FPGA-based balanced processor system for real-time SIFT feature detection, containing a dedicated hardware coprocessor coupled to a custom VLIW soft-core processor using a FIFO memory. The coprocessor calculates the scale-space and performs the extrema detection for the extraction of feature candidates, whereas the VLIW soft-core processor performs sub-pixel localization and stability checks to get stable SIFT-features. The system achieves a peak frame rate of up to 338 fps on 1,024×376 px images at less than 3 W on a Xilinx Virtex-6 FPGA. The filters within the Gaussian pyramid operate in a time-multiplexed scheme on clock frequencies up to 400 MHz. Furthermore, this paper presents a comprehensive design space exploration, evaluating architectural performance, hardware resources and power consumption trade-offs as well as exposing performance-balanced and pareto-optimal design variants. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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